ERICA 소재부품융합 첨단제조장비 혁신인재 교육연구단
The theoretical limit of the subthreshold slope (60mV/dec) in MOSFETs hinders the reduction of power consumption in CMOS integrated circuits. For low power integrated systems in the future technology nodes, a steep slope characteristic is mandatory. In this seminar, I would like to discuss the tunnel field-effect transistor(TFET), which is one of the most promising candidates for realizing the steep slope characteristic. TFETs operate based on the gate-controlled band-to-band tunneling at the PN junction interfaces. III-V compound semiconductors such as InGaAs and InAs have excellent material properties with narrow and direct bandgaps, as well as light tunneling masses. I will address the key issues involved in enhancing the performance of III-V channel TFETs.